I. Field of the Disclosure
The technology of the disclosure relates generally to voltage level shifters for shifting input signals in one voltage domain to output signals in another voltage domain, and particularly to reducing area of voltage level shifters.
II. Background
Processor-based systems may be powered by one or more power supplies, wherein such power supplies provide voltage for processor operations. Particular components within a processor-based system may use less voltage to operate as compared to other components within the same system. For example, a processor in a processor-based system may use less voltage to operate during idle modes, but memory may use a higher minimum voltage to retain data. In this regard, rather than providing a single higher voltage supply to all components in a processor-based system, components of the processor-based system can be configured to operate in multiple voltage domains. Components that operate at a lower voltage are powered by a lower voltage supply in a lower voltage domain, while components that operate at a higher voltage are powered by a higher voltage supply in a higher voltage domain. In this manner, power is conserved as opposed to providing a higher voltage to all components, including components that can operate at a lower voltage.
However, so that signals from components in one voltage domain operating from a first voltage supply can be compatibly provided and processed by components operating from a second voltage supply in another voltage domain, voltage level shifters are employed. Voltage level shifters shift signals from a lower voltage domain to a higher voltage domain, or vice versa. For example, voltage level shifters can shift a logic high (‘1’) voltage in the lower voltage domain (e.g., 0.5 V) to a logic high (‘1’) voltage in the higher voltage domain (e.g., 1.0 V). Voltage level shifters may be implemented using static or dynamic logic. In this manner, static voltage level shifters provide an output signal in response to a change in a state of an input signal. Alternatively, dynamic voltage level shifters change an output signal in response to a change in a state of a clock signal. Conventionally, a dynamic voltage level shifter pre-charges a node to a known voltage during a pre-charge state. The voltage may be held by a keeper circuit or changed by an evaluate circuit during an evaluate state based on a state of an input signal, wherein the voltage on the node is used to produce an output signal of a dynamic voltage level shifter.
Notably, as the difference in supply voltages between the higher voltage domain and the lower voltage domain increases, components within a voltage level shifter are configured so as to reduce or avoid producing erroneous signals. For example, as the difference in supply voltages in the higher and lower voltage domains increases, an input signal in the lower voltage domain may concurrently partially activate an evaluate circuit and a keeper circuit in a dynamic voltage level shifter, potentially leading to erroneous output signals. To prevent such concurrent activation of the evaluate circuit and keeper circuits, the evaluate circuit can be configured to be stronger than the keeper circuit. Conventionally, to configure the evaluate circuit to be stronger than the keeper circuit, the evaluate circuit may be designed with a larger size, thus resulting in an increase in area of the dynamic voltage level shifter. Therefore, it would be advantageous to employ a dynamic voltage level shifter that reduces or avoids producing erroneous signals as the difference in supply voltages of the higher and lower voltage domains increases, while mitigating or eliminating an increase in area.